- Flash technology has proven itself in the role of the high-performance pinnacle of the storage stack, but a few companies are looking to redefine it to accommodate the growing number of large, in-memory applications.
- Upcoming offerings from several vendors are looking to move flash even closer to the compute layer, and this has the potential to remap the traditional CPU/memory architecture in a server near you.
I’ve had the pleasure of attending a number of technology conferences recently, and aside from “hybrid cloud” the one message that crosses over all of them is the overwhelming interest in flash memory technology and how it can improve the performance and flexibility of your data center. We all know that flash isn’t really all that new, flash-based SSDs and memory cards have becoming the de facto storage platform for almost every portable device, but adopting flash for enterprise-level applications has taken a little longer as vendors scrambled to insure that it truly meets the reliability, performance, and cost structure expected for high performance, high duty cycle applications. The obvious first-case applications focused on storage vendors who found that the SSD technology and form-factor was a perfect match for use as a caching layer at the very top of the storage stack in the conventional NAS/SAN model. There were also a few forward-looking vendors like Fusion-IO and OCZ Technologies that chose to decouple flash from the storage bus and upgrade it directly to the PCIe bus.
PCIe is actually an awesome and ubiquitous connectivity option on every motherboard today, but it’s underappreciated in the enterprise and mostly relegated for graphics cards; in spite of the fact that it’s a switchable link capable of up to 128Gb/sec in the PCIe x16 Gen.3 specification (or 16 Gigabytes/sec for you storage guys). Now, that kind of bandwidth is nothing to sneeze at, and it also offers a much closer coupling of high-performance flash capacity to the compute layer by circumventing the slower and chattier storage and network stacks. Unfortunately, most PCIe flash solutions are only single server solutions and don’t necessarily offer the flexibility and economies of scale offered by flash in the context of slower, larger storage architectures. But not for long.
Hence, the next logical progression of flash technology will likely present itself as a new, switchable and manageable layer on a separate interconnect architecture that will offer a combination of rack-level scalability, flexible resource allocation, low-latency and high-performance and will reside below the onboard DRAM memory bus, yet be faster and more versatile than conventional storage solutions. Truth be told, there are actually a number of ways that this can happen. Cisco’s Invicta accelerator technology recently purchased from Whiptail utilizes an InfiniBand backbone that offers a high-performance interconnect that’s switchable, low-latency and benefits from the efficiency of RDMA, but that’s not the only option for rack-level flash. RDMA over Converged Ethernet (RoCE) offers many of the same efficiencies, and it’s worth mentioning that PCIe itself can also serve as a viable, switchable fabric. The challenge isn’t necessarily in the interconnect technology, the bigger issue is just how this new, rack-level flash technology will be managed. It’s not quite storage and it’s not quite system memory, but the good news is this tighter coupling of DRAM and flash in a distributed model will offer a number nifty opportunities for vendors to come up with new and valuable methods for performance tuning and pre-caching, not to mention the opportunity for the introduction of application-specific behaviors that can really make the most of the greatly expanded memory capacity and cost efficiency that flash can offer. Keep your ear to the ground, EMC’s top-secret DSSD technology is on the way too.